摘要
针对USB总线窃听问题,通过深入分析USB传输特性设计实现了一种抗窃听设备控制器。该设备控制器于接口电路与端点缓冲区之间嵌入分组密码模块与端点独立的序列密码模块,使得加/解密能够在数据存取过程中透明进行且支持USB的全部传输方式与多管道应用。接口电路与密码模块设计支持流水传输,基本消除了加/解密对端点缓冲区存取速度的影响。基于FPGA平台对其进行了实现,并结合Nios II片上系统与主机端软件进行了测试。测试结果表明,该设备控制器能够正确地对总线数据进行加/解密,可为各类外设提供抗窃听的USB通信能力。
Through in-depth analysis of USB transfer characteristics, this paper proposed a device controller to against eavesdropping attacks. It supported all transfer types and multi-pipe applications by combining block cipher module and stream cipher module with an endpoint independent design. The cipher modules embedded between the function interface and endpoint buffer could encrypt/decrypt data in the access process transparently. The interface and cipher modules design with pipelined transmission support substantially eliminated the impact of encryption/decryption to endpoint buffer access speed. Its implementation based on FPGA platform has been tested with Nios II system an-chip and host software. The results show that the device controller can correctly encrypt/decrypt the bus data,which means anti-eavesdropping communication capability for USB peripherals.
出处
《计算机应用研究》
CSCD
北大核心
2017年第4期1155-1158,共4页
Application Research of Computers
基金
信息保障技术国防重点实验室开放基金资助项目
河南省科技攻关计划项目(132102210003)