以太网下的基于FPGA的时钟同步策略

Clock Synchronization Strategy Based on FPGA under Ethernet

以太网现场总线技术在高速、高精度、多轴数控加工中具有巨大应用价值,其中分布式时钟的同步精度对加工轨迹和加工精度有着严重的影响。提出一种基于FPGA的以太网现场总线的时钟同步策略。依据IEEE1588原理,阐述了基于FPGA可以更加精确的实现时间戳的捕获;利用PI控制器原理建立时钟同步算法并构建时钟频率补偿模块,可以在较低成本的条件下实现实现高精度时钟同步。在实时以太网通讯协议EtherCAT的组网中,验证时钟同步策略,实验证明,基于FPGA的以太网时钟同步策略使得主从站的同步精度小于100ns,满足高速、高精度、多轴数控加工的精度要求。

Ethernet field bus technology has great application value in the high speed,high precision and multi axis NC machining,and the synchronous precision of the distributed clock has a serious impact on the machining track and machining precision. This paper presents a clock synchronization strategy based on FPGA for Ethernet fieldbus. According to the principle of IEEE1588,elaborated based on FPGA can be more precise realization of timestamp capture; use PI controller theory establish clock synchronization algorithm,and to build a clock frequency compensation module,under the condition of lower cost to achieve high precision clock synchronization is realized. Verification of the clock synchronization strategy in the networking of EtherCAT real-time Ethernet communication protocol. The experiment results showthat the FPGA based Ethernet clock synchronization strategy makes the master and the slave synchronization precision is less than100 ns,which can meet the requirements of high speed,high precision,multi axis NC machining accuracy.