摘要
硅通孔TSV发生开路故障和泄漏故障会降低三维集成电路的可靠性和良率,因此对绑定前的TSV测试尤为重要。现有CAF-WAS测试方法对泄漏故障的测试优于其他方法(环形振荡器等),缺点是该方法不能测试开路故障。伪泄漏路径思想的提出,解决了现有CAF-WAS方法不能对开路故障进行测试的问题。另外,重新设计了等待时间产生电路,降低了测试时间开销。HSPICE仿真结果显示,该方法能准确预测开路和泄漏故障的范围,测试时间开销仅为现有同类方法的25%。
Though silicon via (TSV) open/leakage defect reduces the reliability and yield of three-di- mensional integrated circuits, so pre-bonding TSV tests are especially important. The existing charge and float, wait and sample (CAF-WAS) test method for leakage defect test is superior to other methods such as ring oscillator, etc., however, it cannot test open defect. We propose a pseudo leak path thought to solve this problem. In addition, we redesign a waiting time generation circuit of to reduce the test time overhead. HSPICE simulation results show that the proposed method can accurately forecast the open defect and the scope of the leakage defect with only 25% test time of the existing method [14].
出处
《计算机工程与科学》
CSCD
北大核心
2017年第3期430-435,共6页
Computer Engineering & Science
基金
国家自然科学基金(61674048
61574052
61371025
61474036)