摘要
为有效简化FPGA运算复杂度,降低FPGA处理时钟,在传统的滑动窗相关的基础上,结合1bit量化方法及多径能量积累的抗多径算法,提出了一种基于1bit量化的超宽带多路并行同步方法,在此基础上设计了FPGA实现方案.推导分析了1bit量化同步方法对系统性能的影响,给出了信噪比损失的量化结果.仿真结果表明,在低信噪比条件下,1bit量化方法引入2dB的信噪比损失.在高斯信道和瑞利信道下,通过针对虚警概率和漏检概率的分析及仿真,找到最优门限范围.
In order to simplify the complexity and reduce clock of field programmable gate array（FPGA）,an improved multi-channel parallel synchronization scheme was proposed based on traditional sliding window correlation,combining the 1bit quantification and multipath energy accumulation algorithm.In this paper,a method was designed to implement the FPGA,the influence of 1bit quantification on system performance was analyzed and the quantitative results of SNR loss was provided.The simulation results show that the 1bit quantification can bring 2dB SNR loss in Gaussian and Rayleigh channel.The best threshold range can be got through the simulation of false alarm probability and detection probability in Gaussian and Rayleigh channel.
作者
聂青
方宁
徐湛
高飞
杨博
NIE Qing FANG Ning XU Zhan GAO Fei YANG Bo(School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China School of Information and Communication Engineering, Beijing Information Science and Technology University, Beijing 100192, China)
出处
《北京理工大学学报》
EI
CAS
CSCD
北大核心
2017年第2期175-179,共5页
Transactions of Beijing Institute of Technology
基金
国家自然科学基金资助项目(61301089 61402044)
国家部委"八六三"计划项目(2015AA01A706)
北京市教委科研计划资助项目(KM201511232011)
北京市科技新星计划资助项目(Z161100004916086)
关键词
1bit量化
多路并行
同步
高斯信道
瑞利信道
信噪比
1bit quantification
multi-channel parallel
synchronous
Gauss channel
Rayleigh channel
SNR
