基于FPGA的素数域模乘算法的高效实现

Efficient implementation of modular multiplier on FPGA

为了提高素数域模乘算法在FPGA上的实现效率,本文提出了一种高效的设计方案来完成256*256位模乘法算法。分析蒙哥马利模乘算法特点,利用Xilinx FPGA内部模数IP内核资源设计了512位加法器和256*256位模数乘法器,本文设计的蒙哥马利模乘器相比传统的方案运行效率提高将近50%,这在硬件实现中具有重要意义。

To improve the efficiency of prime number modulo multiplier for FPGA implementation, this paper proposes an efficient design scheme to accomplish the 256＊256 bits modular multiplication algorithm. Based on the analysis of the principle of Montgomery modular multiplication algo- rithm, The Xilinx FPGA internal modulo IP core resources are utilized to design 512-bit adder and 256＊256 bit modulus multiplier, compared with the traditional modulus multiplier method, This scheme＇ s Montgomery running efficiency is improved 50%, which is of great significance in the hardware implementation.