摘要
针对当前NAND Flash存储结构的特性,提出一种纠错能力较强的ECC校验电路结构,设计一种高效并行的BCH编译码器的电路,在关键方程计算过程中采用了无求逆的BM算法,避免了迭代过程中的有限域求逆运算。通过流水线技术与乒乓操作技术,实现以较小的硬件资源开销提高纠错电路的数据吞吐性能。该ECC纠错电路在Xilinx Vivado上进行仿真,并测试分析。通过测试可以发现,在相同的系统时钟频率下,该ECC纠错电路的数据吞吐率是典型串行纠错电路的8倍,并且通过两级流水线的译码方式,使得译码速度得到大幅度提升,很好地提高了译码效率,同时纠错能力能够满足当前NAND Flash技术的要求;与传统的NAND flash纠错电路相比,该纠错电路结构可移植性强,并且灵活性较强,通过调整BCH码的校验位数目,即可满足不同的纠错要求。
A high-performance error correcting circuit is presented for NAND Flash memory. Hereinafter, An efficient parallel BCH codec is brought up, and an inversionless BM is adopted to solve the critical equation without finite field inverse operation. Based on the combing pipeline technology and ping-pong operation technology, the performance of the correcting system is improved ingeniously while the increasing cost is acceptable. The error correcting system circuit is simulated, implemented and tested on Vivado platform. Under the same system operating frequency, eight times greater data throughput rate are achieved than those of the traditional serial circuits. And the decoding rate owes a highly improvement to two-level pipeline operation while the correcting performance is up to present NAND Flash technical standard. In comparison with traditional NAND Flash error correcting circuit, this error correcting circuit is relatively flexible and portable, and can meet the requirements of various correcting systems by adjusting parity bits.
出处
《电子测量技术》
2017年第3期127-132,共6页
Electronic Measurement Technology
