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基于CMOS工艺的负压低压差线性稳压器设计

Design of a Negative Voltage Output LDO for RF Power Amplifier Applications
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摘要 设计了一种应用于射频功放的负压低压差线性稳压器。通过设计负压带隙基准源,以及采用预稳压模块,有效地降低了电源电压对负压LDO输出电压的影响;通过优化控制环路中的功率管尺寸、误差放大器以及电阻反馈网络等措施,在保证大电流输出的前提下,有效地降低了负压LDO的压差,提高了稳压器的整体性能。采用CSMC 0.5μm CMOS工艺进行设计并实现,测试结果表明,当输出电流为500mA,输出电压为-3V时,压差仅为170mV。 A novel negative voltage output LDO was designed,which can be used in radio frequency power amplifier electrical systems.A negative bandgap reference and a pre-regulator circuit module were adopted which may reduce the effect of supply voltage on output voltage.The width and length of the output transistor and the value of the feedback resistor were optimized,and an error amplifier was redesigned which may effectively reduce the dropout voltage of the negative LDO.This LDO was realized by CSMC 0.5μm CMOS process.Test results show that when the current load is 500 mA and the output voltage is-3V,the dropout of this LDO is only170 mV.
出处 《固体电子学研究与进展》 CAS CSCD 北大核心 2016年第3期234-239,共6页 Research & Progress of SSE
基金 国家科技重大专项资助项目(2016ZX03001005) 国家自然科学基金资助项目(61366006)
关键词 负压低压差线性稳压器 负压基准源 低压差 误差放大器 过温保护 negative voltage output low-dropout regulator(LDO) negative voltage output BGR low dropout error amplifier over-temperature protection
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