单精度浮点数FFT的FPGA实现

Implementation of FPGA for single precision floating point FFT

文中首先讨论了多种FFT算法及其基本原理,实现了基2频率抽取算法,采用单蝶形顺序处理的结构实现单精度浮点数FFT处理器。根据自顶向下的设计思想,将整个设计划分为6个子模块,分别对子模块进行设计,最后组合成FFT处理器。然后,文中介绍了浮点数加法器和浮点数乘法器的硬件实现,在其中引入流水线,大大提高了数据吞吐量,提高处理速度。在中间结果缓存单元的设计中,调用Altera IP Core中的三口RAM,能够同时读写数据,大大节省了运算时间。最后对FFT处理器进行了功能仿真和时序仿真,做了详尽的分析测试。结果表明,单精度浮点数FFT处理器达到了较高的运算精度,可稳定运行在62.5MHz,完成一次256点浮点数复数FFT运算需要33.056μs。与DSP和单片机实现的FFT相比,在性能上具有一定优势。

Firstly,this paper discusses a variety ol FFT algori thm and its basic principles,analyzes the lour hardware structure to realize FFT. Finally,it selects radix-2 decimation in frequency algorithm and the structure ol a single butterfly processed in the order to realize single precision floating point FFT processor. According to the top-down design idea,the whole design is divided into six sub-modules. It designs each sub-module,combines six sub-modules to form FFT processor at last. Then,it describes the hardware implementation of floating point adder and floating point multiplier. Leading pipeline into them greatly improves data throughput capacity and increases processing speed. The design of cache units of intermediate results, cal l the three Al tera IP Core t ri -port RAM , ca n read and w r i te d a ta at th e same time, saving computing time. The FFT processor passes the function simulation and timing simulation, i t made a detailed analysis of the test. The result shows that single precision floating point FFT processor achieved higher computing accuracy,stability running at 62. 5MHz. A completed 256-point floating point complex FFT operation takes 33. 056us. FFT based on FPGA has certain advantages in performance compared with the DSP and MCU.