CIC滤波器改进及其FPGA实现

The improvement of CIC Filter and its implementation on FPGA

在分析多级CIC滤波器结构和特性的基础上,阐述了一种利用Hogenauer"剪除"理论通过消除来自前级的一些较低有效位来提高CIC滤波器性能,并完成多级CIC滤波器的高效FPGA实现方法.通过QuartusⅡ时序仿真分析验证了该方法的正确性和可行性,能够满足现代移动通信系统要求,提高了系统运算效率.通过对内部寄存器的位宽进行改进,极大地节约了硬件资,提高了系统运行速率.

On the basis of analysis of the structure and characteristics of the multi-stage CIC filter,elaborate an efficient FPGA implementation method which use the Hogenauer＂cut off＂theory that is can eliminate some of the less significant bits from the former class to improve the CIC filter performance,and finish the completion of a multi-stage CIC filter.Using the timing simulation analysis of Quartus Ⅱ can verify the correctness and feasibility of the method,and meet the requirements of modern mobile communication system,improve the system operation efficiency.By improving internal register bits wide,it can greatly saves hardware resources and improves the system running speed.