数据中心中DVFS对程序性能影响模型的设计

Modeling the Impact of DVFS on Performance of Applications in Datacenter

数据中心以可接受的成本,承载着超大规模的互联网应用.数据中心的能源消耗直接影响着数据中心的一次性建造成本和长期维护成本,是数据中心总体持有成本的重要组成部分.现代的数据中心普遍采用动态电压频率调节(dynamic voltage frequency scaling,简称DVFS)来提升单节点的能耗表现.但是,DVFS这一类机制同时影响到应用的能源消耗和性能,而这一问题尚未被深入探索.专注于DVFS机制对应用程序性能的影响,提出了一个分析模型用来量化地刻画应用程序的性能与处理器频率之间的关系,可以预测程序在任意频率下的性能.具体来说,依据执行时访问内存子系统资源的不同,把程序的指令分为两部分——片上指令和片外指令,并分别独立建模.片上指令是指仅需访问片上资源就可以完成执行的指令,其执行时间与处理器频率呈线性关系;片外指令是指需要访问主存的指令,其执行时间与处理器频率无关.通过上述划分和对每一部分执行时间的分别建模,可以获得应用程序的执行时间与处理器频率之间的量化模型.使用两个不同的平台和SPEC 2006中的所有标准程序验证该模型,平均误差不超过1.34%.

Datacenters are built to house massive internet services at an affordable price.Both Op-ex （long-time operational expenditure） and Cap-ex （one-time construction costs） are directly impacted by datacenter power consumption.Thus,DVFS （dynamic voltage and frequency scaling） is widely adopted to improve per node energy efficiency.However,it is well known but has not yet been fully explored that such schemes affect an application＇s power consumption and performance simultaneously.This paper focuses on the impact of DVFS on performance of an application and proposes an analytical model to quantitatively characterize the relationship between an application＇s performance and a processor＇s frequency,which can be leveraged to predict the performance of an application at any frequency.Specifically,according to different memory subsystem resources accessed,instructions of an application are divided into two parts：on-chip instructions and off-chip instructions,which can be modeled independently.On-Chip instructions refer to instructions which only access on-chip resources,and their execution time is frequency-relevant and can be modeled using a linear function.Off-chip instructions stand for instructions accessing the main memory,and their execution time is dominated by memory access latency and is frequencyirrelevant.By the division and modeling of the two parts,a quantitative model can be obtained between the execution time of an application and frequency of a processor.Evaluations using two different platforms and all benchmarks of SPEC 2006 show that the derived models are very precise,with average prediction error less than 1.34%.