一种基于CMOS工艺的异步数字斜坡ADC

An Asynchronous Digital Slope ADC Based on CMOS Technology

设计了一个5位330 MS/s的异步数字斜坡模数转换器(ADC)。采用中芯国际55nm工艺和Cadence Virtuoso软件,对电路进行设计和仿真。供电电源为1.2V,改进后的延迟单元将延迟时间缩短到50ps。另外,该电路中的比较器采用自动关闭方式,节省了功耗。输入电压峰峰值为0.4V时,仿真得到信噪失真比(SNDR)为28.19dB,有效位(ENOB)为4.39位,无杂散噪声动态范围(SFDR)为35.87dB,信噪比(SNR)为31.47dB。

A 5-bit 330 MS/s asynchronous digital slope ADC was designed. All circuits were implemented and simulated with Cadence Virtuoso tool in SMIC 55 nm CMOS technology. The power supply was 1.2 V and the improved delay cells were used to shorten the delay time to 50 ps. In addition, a self-disabled eomparator was used to save the power. The simulation results showed that the proposed circuit achieved an SNDR of 28.19 dB, an ENOB of 4.39 bit, an SFDR of 35.87 dB, an SNR of 31.47dB when the peak-to-peak value of input was 0.4 V.