FFT算法硬件模块的高层次综合实现与优化

FFT Hardware Implementation and Optimization with High-Level Synthesis

针对传统硬件描述语言对模型和算法的结构调整及优化结果对比存在难度大、开发周期长等不足,提出了利用高层次综合的方法进行算法的硬件模块设计。以基于时间抽取的16点基-2FFT为例,利用C语言对算法进行描述,通过循环展开、数组分割、乘法简化、单个时钟周期长短调整等优化方式对设计结果进行探索。探索结果表明,通过更改C语言数据类型和代码结构,能够快速实现不同性能要求的硬件方案设计,与传统寄存器传输级(RTL)实现相比,大大降低了算法模块的设计难度,缩短了开发周期,便于探索硬件设计过程中的各种可能性。

In the view of the difficulties of using traditional hardware description language in modeling and algorithm description,such as the difficulty to compare structural adjustment and optimization results as well as the long developing cycle,a high-level synthesis method was proposed to design the algorithm hardware block.A time sampling based 16 point radix-2FFT was taken as an example,and the algorithm was descriped by C language.The impacts of loop unrolling,array partitioning,multiplex simplifying,single clock adjustment on the design results were fully evaluated.The results showed that the hardware scheme could be fast implemented for different performance requirements by changing the C language＇s data type and code structure.Compared with traditional register transfer level（RTL）designs,the design difficulty of algorithmic hardware block was reduced,and the developing cycle was shortened.It was convenient to explore the possibilities of hardware block design.