电路抗老化设计中基于门优先的关键门定位方法

A Method to Identify Critical Gates by Prioritizing Logic Gates Under Circuit Anti-Aging Design

随着CMOS工艺尺寸不断缩小,尤其在65nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。

With the continuous reduction of CMOS transistor dimensions, especially in 65 nm CMOS process and below, negative bias temperature instability has become an important factor for the CMOS device reliability. A new method for identifying critical gates by prioritizing logic gates was proposed. The proposed method was based on a static timing analysis framework of NBTI. The logic gates from the aging-sensitive of paths were preferred in the circuit, and then the path correlation was analyzed to identify the critical gates. Compared with similar methods in the same conditions of experimental environment, experimental results on ISCAS benchmark circuits in a 45 nm CMOS process showed that the number of the positioning key door was much less, and the improvement rate of critical path delay was greatly increased. The method effectively reduced the design cost of expenses.