一种载波通信SOC信道交织/解交织器设计

Design of One Kind of Channel Interleaver/Deinterleaver in the Carrier Communication SOC

基于HomePlug AV协议设计了一款在电力线载波通信SOC芯片中得到广泛应用的信道交织/解交织器,通过设置不同的文件顶层配置参数,可以使交织/解交织器以半双工方式工作在芯片中.该设计通过算法实现、寄存器级(RTL)设计并进行ModelSim和Synopsys仿真及DC综合后仿,成功地证明了设计的正确性.在100 MHz工作频率下运用DC综合工具进行时序时序分析可以得知,slack(MET)为2.45,面积为22 702.048 020μm^2,功耗为658.043 4μW.

On the basis of HomePlug AV socket protocol, designed a kind of Channel interleaver/deinterleaver is designed which can apply in the power line carrier communication SO（; chip. By setting the top configuration parameters for different files, we can get the half duplex mode working of channel interleaver / deinterleaver in the chip. Through the algorithm and RTL design and ModelSim subsequent Synopsys composite tools DC; comprehensive simulation, verify the correctness of the design. The timing results show that at 100 MHz clock, slack（MET） is 2.45,the total cell area： is 22 702. 048 020 μm2 ,and the power estimation results are 658. 043 4 μW.