摘要
对前导数字预测算法的误差修正逻辑进行分析改进和设计实现,重点对该误差修正纠错模块的逻辑设计进行了分析证明,依据设计的逻辑表达式对其电路进行了设计.同时采用硬件描述语言VerilogHDL编程,结果使用QuartusⅡ进行仿真验证.使用性能分析软件对提出的纠错逻辑方案进行验证,可以看出本纠错单元的电路在电路面积和功耗上都有明显的改善.
In this paper, we put forward a novel design of the error correction logic . At the same time, we also design the circuit and programed it with Quartus Ⅱ. At the end of the article we also give the verification and simulation results. The results of the performance analysis tools show that the error correction circuit we put forward in this article improved significantly in the circuit area and the power.
出处
《微电子学与计算机》
CSCD
北大核心
2017年第5期67-72,共6页
Microelectronics & Computer
基金
国家自然科学基金(51577131)
