粗粒度可重构SoC层次化配置存储器设计

Hierarchical Configuration Memory Design for Coarse-Grained Reconfigurable SoC

配置信息的生成效率与质量直接影响着粗粒度可重构SoC结构的运行效果.传统的方法将配置信息作为一个整体存储器,每个处理单元在需要配置信息时都要从该存储器读取配置信息,运行效率低下且功耗较大.为降低配置信息生成方法的功耗,设计了一种低功耗层次式的配置信息存储器结构,将配置信息分为相互独立的操作配置信息和互连配置信息存储器两部分,实现了不同层次上的重构,最后根据上下文优化配置信息生成.实验结果表明:在运行性能不变的情况下,提出的配置信息生成方法功耗可以减少23.7%~32.6%.同时,由于操作和互连配置信息相分离,使得每次需要配置的存储器容量较小,在配置速度和性能上也有很大的优势.

The generate efficiency and quality of configuration information directly affect the operation effect of the coarse grained reconfigurable SoC. Since the traditional approach treats the configuration memory as a whole, and each processing unit needs to read configuration information from the memory, the operation efficiency is low and the power consumption is large. In this paper, a low power hierarchical configuration information storage architecture is designed, which divides configuration information into separate operating configuration information and interconnect configuration information, and then generates the configuration information based on the context. Experimental results show that the configuration information generation method proposed in this paper can reduce power consumption of 23. 7%-32. 6% while keeping the same performance. At the same time, because of the separation of the operation and the configuration information？ the configuration information capacity is small,so it has a great advantage in configuration speed and performance.