硬件友好的3GPP-LTE Turbo交织器设计

Design of a hardware-friendly turbo interleaver for 3GPP-LTE

研究了第三代合作伙伴计划长期演进技术(3GPP-LTE)中的二次置换多项式(QPP)交织器的硬件设计优化,提出了一种零延时、低复杂度的QPP交织器设计方案。该方案从算法层面出发简化了QPP交织器中定义的复杂运算。得益于算法优化的结果,优化后的QPP交织器能够以较低的代价映射到硬件电路上。结果表明:与一些传统方案相比,该方案设计的QPP交织器大大降低了硬件实现的复杂度,在SMIC 40nm工艺下,交织器的面积只有0.040mm^2。另外,所设计的QPP交织器具有零时延的特点,能够有效提高Turbo译码的译码效率。基于该交织器所设计的Turbo译码器能够稳定工作在400MHz下,译码速率达到572.85Mbps(10次半迭代),而译码器面积仅有0.82mm^2。

The optimization of the hardware design of quadratic permutation polynomial （QPP） interleavers for 3GPP-LTE was studied, and a scheme for design of zero-delay, low-complexity QPP interleavers was presented. The design scheme can simplify the complex computations defined by OPP interleavers at the algorithm level, and it makes an optimized OPP interleaver be readily mapped onto its hardware circuit under a low cost because of the benefit from the optimization. The implementation result shows that the proposed scheme can greatly reduce the complexity of hardware implementation compared to traditional approaches, and the area of the designed interleaver is only 0. 040mm2 under the technology of CMOS 40mm. Furthermore, the designed interleaver reveals its zero-delay prop- erty, and the ability to effectively improve the efficiency of Turbo decoding. Actually, after putting the whole Turbo decoder into practice, the decoder can work at 400 MHz, the area of which is only 0.82ram2 while the peak deco- ding throughput can reach 572.85Mbps with 10 half-iterations.