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面向系统吞吐量与公平性的存控调度算法综述

SUMMARIZE OF STORAGE CONTROLLER SCHEDULING ALGORITHM FOR THROUGHPUT AND FAIRNESS
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摘要 现代处理器多使用片外存储器动态随机存储器DRAM(Dynamic Random Access Memory),但受到工艺限制,对片外存储器的存储速度一直是制约处理器性能的瓶颈。存储控制器作为处理器芯片与片外存储器的接口,使用的调度算法会对访存性能产生直接且关键的影响。针对现代DRAM的结构,以及几种典型的面向系统吞吐量与公平性的存控调度算法,对这些算法各自的优势与劣势作了简要分析,提出有待改进的地方。通过对面向系统吞吐量与公平性的存控调度算法的设计框架作一般化分析,得出新算法的设计与优化的方向。 Modern processors use off-chip memory DRAM,but by the process limitations,off-chip memory storage speed has been the bottleneck of processor performance constraints. As the interface between the processor chip and its off-chip memory,the storage controller uses the scheduling algorithm to have a direct and critical impact on the access performance.Aiming at the structure of modern DRAM and several typical storage controller scheduling algorithms for system throughput and fairness,the advantages and disadvantages of these algorithms are briefly analyzed,and some improvements are proposed.Through the general analysis of the design framework of the storage controller scheduling algorithm for the throughput and fairness of the system,the direction of the design and optimization of the new algorithm is obtained.
出处 《计算机应用与软件》 2017年第5期273-278,共6页 Computer Applications and Software
关键词 DRAM 存储控制器 多核调度算法 系统吞吐量 公平性 DRAM Storage controller Multi-core scheduling algorithm System throughput Fairness
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  • 1Nesbit K J,Aggarwal N,Laudon J,et al.Fair queuing memorysystems. MICRO-39 . 2006
  • 2Mutlu O,Moscibroda T.Stall-time fair memory access scheduling forchip multiprocessors. MICRO-40 . 2007
  • 3Moscibroda T,Mutlu O.Memory performance attacks:Denial ofmemory service in multi-core systems. Proceedings of 16thUSENIX Security Symposium on USENIX Security Symposium . 2007
  • 4Binkert N,Dreslinski R,Hsu L,et al.The M5 simulator:modelingnetworked systems. Micro IEEE .
  • 5Rixner S,Dally WJ,Kapasi UJ,et al.Memory access scheduling. Proceedings of the 27th Annual International Symposium on Computer Architecture . 2000
  • 6Demers A,Keshav S,Shenker S.Analysis and simulation of a fair queueing algorithm. Proc. of the ACM SIGCOMM’89 . 1989
  • 7Mutlu O,Moscibroda T.Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems. Proc. ISCA 2008 . June21–252008
  • 8Wang D,Ganesh B,Tuaycharoen N,et al.DRAMsim: a memory system simulator. ACM Computer Architecture News . 2005

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