中子数字成像FPGA抗辐照技术研究

Radiation hardening techniques for neutron digital imaging FPGA

中子数字成像试验中,现场可编程门阵列(FPGA)是重要的成像逻辑控制器件。然而,中子辐照易引起FPGA的单粒子效应,对中子成像引入本底噪声,因此必须采取措施,减少中子辐照对FPGA成像的影响。结合图像周期性的特点,采用三判二的技术方法替代三模冗余,裁决成像关键信号;采用硬件实现的中值滤波算法,平滑由于RAM区单粒子翻转等原因呈现在图像上的噪点。仿真结果表明,本文采用的两种技术方法不但降低资金成本,提高FPGA资源冗余度,而且在取得良好的抗辐照滤波效果的同时,保留图像细节。时序仿真和硬件平台验证了设计的正确性。

In neutron digital imaging experiments, field programmable gate array （FPGA） is an important logic control unit for imaging. However, neutron irradiation can not only cause single event effects of FPGA, but also bring noises to neutron imaging. It is necessary to take measures to reduce the effects of neutron irradiation on FPGA imaging. In this paper, based on the periodical characteristics of images, a method of ＂two vote from three＂ instead of triplet modular redundancy is adopted to judge imaging key signals. The noises which are caused by many reasons including the single event upset（SEU） in RAM area can be smoothed by using median filter algorithm with hardware implementation. The simulation results show that two techniques and methods used in this paper not only achieve the resource redundancy and cost saving of FPGA, but also get good anti-radiation filtering effect, while preserving image details. Timing simulation and hardware platform have verified the correctness of the design.