32位稀疏树可逆逻辑加法器的Verilog设计

A 32-bit Sparse-tree Reversible Logic Adder Designed by Verilog

本文根据现提出基于量子计算可逆逻辑设计的基本原则,参考已有基本可逆逻辑门结构,完成4位串行加法器模块、4位选择器模块、进位产生与进位传播模块、基2点操作模块、进位输出模块等可逆逻辑模块的Verilog设计。提出一种基于基二稀疏树的改进型32位全加器结构,基于前述模块完成加法器设计,并通过功能验证。

This paper completes the reversible logic modules＇ design by Verilog such as, 4-bit serial adder, 4-bit selector, carry output and carry generation, point operation and carry output, and so on, based on the basic principle of reversible logic design for quantum computation and existing reversible logic gate structure. It presents a improved 32-bit full adder structure based on the 2-bit sparse tree, and passes functional verification. designs the adder using these modules we have completed