用于DP-QPSK系统的高速ADC的验证方法

Evaluating high-speed ADC in DP-QPSK system

介绍了一种在高速相干光通信系统中验证模数转换芯片(ADC)的方法。该方法将待测ADC的数据导入Optisystem软件中对112Gb/s双偏振正交相移键控(DP-QPSK)的系统进行仿真。验证了该方法的可行性,并对33GS/s 6比特的ADC的光信噪比(OSNR)容限测试结果进行了讨论。

This paper introduces an approach for evaluating the performance of the analog-to-digital convertor （ADC） in high speed coherent optical communication system. This approach imports the data generated from ADC under test to Optisystem to simulate in 112Gb/s DP-QPSK system. The feasibility of the approach has been verified and the testing results of optical-signal-noise-ratio （OSNR） tolerance with a 33GS/s 6bit ADC have been discussed.