高性能集成锁相环中低失配电荷泵的设计

Design of a Low-spur Charge Pump for High Performance CMOS Phase-locked Loops

在分析电荷泵结构、工作原理和产生杂散机理的基础上,该文提出了一种低静态电流失配、低时序失配的高性能电荷泵。此电荷泵通过减小电荷泵开关过程中时序失配和电流失配,减小了高频锁相环中的抖动和杂散。基于中芯国际0.18μm CMOS射频工艺技术和1.8 V电源电压,对采用此高性能电荷泵的锁相环进行了相位噪声仿真。仿真结果验证了这些锁相环具有低噪声特性:在480 MHz的输出频率下,二阶锁相环的周期抖动为1.05 ps,最大参考杂散为-121 dBc。

On the basis of the analysis of the structure, operation principle and mechanism of generating spurs of the charge pump, a charge pump with a low static current mismatch and a low timing mismatch is proposed. This charge pump suppresses the jitter and spurs in high-speed Phase-Looked Loops （PLL） by improving the timing mismatch and the current mismatch during switching in the charge pump. Based on the SMIC 0.18μm CMOS radio frequency technology with 1.8 V power supply, the phase noise simulation of the PLLs adopting the proposed charge pump is performed. The simulation results demonstrate that those PLLs achieve a low noise performance： the second-order PLL shows a period jitter of 1.05 ps and the largest reference spur of -121 dBc with the PLL output frequency of 480 MHz.