摘要
针对TMS320C6678多核DSP和RapidIO接口在雷达、声纳、通信等领域的广泛运用,以及RapidIO接口在不同处理器中实现的差异性和应用的复杂性,重点研究RapidIO接口在多核DSP与FPGA之间的通信接口设计。以RapidIO接口在TMS320C6678与FPGA中的组织结构为基础,研究两者的通信方式、配置方式与触发方式,设计出适合阵列信号处理系统的RapidIO接口应用实例,并在某前视声纳系统中对本设计方案的正确性和实用性进行了验证。
Considering the fact that multi-core DSP TMS320C6678 and RapidIO interface are broadly applied in the area of Radar, Sonar and Communication, as well as the problem that the implementation and application of RapidlO is different and complicated in different processors, the RapidlO communication interface of between multi-core DSP and FPGA is studied and designed. Based on their structures, the pattern of communication, configuration and trigger of RapidlO of between TMS320C778 and FPGA are researched. The application instance of RapidlO interface fit for array signal processing system is designed, and verified in certain FLS system.
出处
《通信技术》
2017年第5期1060-1065,共6页
Communications Technology
