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利用拥塞信息片上网络自适应容错路由算法 被引量:1

A Link Fault Tolerant Routing Algorithm with Congestion Information Awareness for NOC
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摘要 3D片上网络(NoC)可以为高性能的片上系统(SoC)提供有效可扩展的通信架构。针对3D NOC架构的可靠性易受运行错误影响的问题,提出一种近邻拥塞信息感知的自适应容错路由算法(FT-DyXYZ),根据邻近拥堵信息来平衡网络中的负载,利用自适应路由算法选择轻拥堵无故障的最短路径进行数据传输。该算法无需路由表、冗余信息、路径和错误的全局信息,大大降低了计算开销。在不同负载模式和错误链接率的情况下进行实验,结果表明,相比平面自适应路由算法,FT-DyXYZ在延迟、饱和注入率和投递率等性能方面具有显著优势。 Three dimensional Network-On-Chips (NOC) have emerged as the most efficient and scalable communication structures for complex and high performance System-on-Chips (SOC). For the issues that the 3D NOC are so susceptible to runtime faults. A link fault tolerant routing algorithm with congestion aware (FT-DyXYZ) is proposed, it uses proximity congestion information to balance traffic, and uses the adaptive routing algorithm to choose the shortest path which light congestion to transfer data. It achieves fault tolerance without using routing tables, redundancy or global information of paths and faults, greatly reduces the computational overhead. The experiment is carried out at different load patterns and the error rate of the link, the results show that, compared with the planar adaptive routing algorithm, FT-DyXYZ shows excellent performance in delay, saturation injection rate and delivery rate.
作者 杨祥 毕朝国
出处 《控制工程》 CSCD 北大核心 2017年第6期1218-1223,共6页 Control Engineering of China
基金 江苏省高校自然科学研究面上项目(14KJB520014)
关键词 3D片上网络(NoC) 链路容错路由 最短路径 拥塞感知 自适应 片上系统(SoC) Three dimensional Network-on-Chip (NoC) link fault tolerant routing shortest path congestion perception adaptive System-on-Chip (SoC)
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  • 1欧阳一鸣,刘蓓,齐芸.三维片上网络测试的时间优化方法[J].计算机研究与发展,2010,47(S1):332-336. 被引量:4
  • 2李德毅,刘常昱,杜鹢,韩旭.不确定性人工智能[J].软件学报,2004,15(11):1583-1594. 被引量:398
  • 3王颀,单智阳,朱云涛,邵丙铣.串扰约束下超深亚微米顶层互连线性能的优化设计[J].电子学报,2006,34(2):214-219. 被引量:4
  • 4B S Feero,P P Pande.Networks-on-chip in a three-dimensional environment:A performance evaluation[J].IEEE Transactions on Computers,2009,58(1):32-45.
  • 5J D Owens.Research challenges for on-chip interconnection networks[J].Micro,2007,27(5):96-108.
  • 6D Fick,D A Andrew,et al.Vicis:a reliable network for unreliable silicon[A].Proceedings of Design Automation Conference 2009[C].San Francisco:ACM,2009.812-817.
  • 7G Cristian,P Pande,et al.Methodologices and algorithms for testing switch-based NoC interconnects[A].Proceedings of International Symposium on Defect and Fault Tolerance in VLSI System[C].Monterey:IEEE,2005.238-246.
  • 8Chao-chao Feng,Zhong-hai Lu,et al.A low-overhead faultaware deflection routing algorithm for 3D NoC[A].Proceedings of IEEE Computer Society Annual Symposium[C].Chennai:IEEE,2011.19-24.
  • 9N Rameshan,V Laxmi,et al.Minimal path,fault tolerant,QoS aware routing with node and link failure in 2-D mesh NoC[A].Proceesings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems[C].Kyoto:IEEE,2010.60-66.
  • 10A DeOrio,D Fick,et al.A reliable routing architecture and algorithm for NoCs[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2012.31 (5):726-739.

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