基于FPGA的高速模糊控制器设计与实现

Design and implementation of a high-speed fuzzy controller based on FPGA

为了提高模糊控制器的响应速度,提出了一种基于FPGA的高速模糊控制器设计方案。该方案采用了5级流水线结构:第一级计算期望值与实际值的差值,第二级得到精确的差值e与ec,第三级对其模糊化得到模糊值E与EC,第四级对前一级输出查表得到模糊输出U,第五级解模糊得到精确输出u。该方案在Vertex-II FPGA上运行时钟频率达到100 M,适用于对响应速度敏感的控制领域。通过对该模糊控制器的matlab以及电路的仿真,验证了其功能的正确性,达到预期的设计效果,具有较高的应用价值。

In order to improve the response speed of the fuzzy controller, this paper presents the design of a high-speed fuzzy controller based on FPGA. The program uses five pipeline structure. The first stage calculate the difference between the expected value and the actual value. The second stage get accurate value of e and ec, then the third stage get it＇s fuzzy values E and EC. The fourth stage look up the value of the third stage from a look-up table and get the fuzzy output U. Finally, the fifth stage get the accurate output u . This program runs on Vertex -II FPGA frequencies up to 100 M, suitable for sensitive response speed control domin. This paper describes the design and simulation of the fuzzy controller with matlab. Then show circuit simulation to verify the correctness of its functions and finally achieve the desired results, having a high market value.