期刊文献+

片上网络映射优化问题研究与进展 被引量:1

Study of mapping optimization in network-on-chip
下载PDF
导出
摘要 映射优化问题是片上网络关键技术之一,其模型的建立及求解影响着片上网络性能。映射问题被证明是NP问题,传统求解具有一定的难度,大多采用启发式算法完成。为了解当前映射优化问题研究现状及发展前景,针对片上网络IP核到网络节点的匹配优化问题进行建模和分类,并对当前研究中的一些典型映射算法在目标、约束条件、性能、采用拓扑结构等方面进行对比分析,最后给出片上网络中映射优化问题未来的研究方向。 Mapping optimization problem is one of the key technologies of network-on-chip (NoC) and the solutions of the mapping modeling have important influence on the performance of NoC. Solving the mapping problem which has been proved to be a NP hard problem with traditional methods is difficult so that heuristic algorithms are adopted instead. To find out the present situation and future development in mapping optimization, this paper proposed a general mathematical optimization model and classified the mapping problem of intellectual property (IP) cores map to the nodes on NoC architecture. Then it proposed a number of the typical solution’s analysis and comparison about current mapping algorithms in the view of targets, constraints, performances and topologies. Finally, it presented the further research directions of mapping optimization on NoC.
出处 《计算机应用研究》 CSCD 北大核心 2017年第7期1929-1934,共6页 Application Research of Computers
基金 国家自然科学基金资助项目(61472300)
关键词 片上网络 映射优化 启发式算法 network-on-chip(NoC) mapping optimization heuristic algorithm
  • 相关文献

参考文献11

二级参考文献136

  • 1周干民,尹勇生,胡永华,高明伦.基于蚁群优化算法的NoC映射[J].计算机工程与应用,2005,41(18):7-10. 被引量:14
  • 2吴春明,陈治,姜明.蚁群算法中系统初始化及系统参数的研究[J].电子学报,2006,34(8):1530-1533. 被引量:47
  • 3张磊,李华伟,李晓维.用于片上网络的容错通信算法[J].计算机辅助设计与图形学学报,2007,19(4):508-514. 被引量:18
  • 4Dally W J and Towles B. Route packets, not wires: on-chip interconnection networks [C]. Proceedings of Design Automation Conference, Las Vegas, Nevada, 2001: 683-689.
  • 5Bertozzi D, Jalabert A, Murali S, et al. NoC synthesis flow for customized domain specific multiprocessor systems-on-chip[J]. IEEE Transactions on Parallel and Distributed Systems, 2005, 16(2): 113-129.
  • 6Hu J C, Shin Y, Dhanwada N, et al. Architecting voltage islands in core-based system-on-a-chip designs [C]. Proceedings of the 2004 International Symposium on Low Energy Electronics and Design, Newport Beach, 2004: 180-185.
  • 7Ogras U Y, Marculescu R, Marculescu D, et al. Design and management of voltage-frequency island partitioned networks -on-chip[J]. IEEE Transactions on Very Large Scale Integration ( VLSI) Systems, 2009, 17(3): 330-341.
  • 8Seiculescu C, Murali S, Benini L, et al. Comparative analysis of NoCs for two-dimensional versus three- dimensional SoCs supporting multiple voltage and frequency islands[J]. IEEE Transactions on Circuits and Systems Ⅱ. Express Briefs, 2010 ,57(5): 364-368.
  • 9Ogras U Y, Marculescu R, Choudhary P, et al. Voltage- frequency island partitioning for GALS-based networks-on- chip[C]. Proceedings of the 44th Annual Conference on Design Automation, San Diego, 2007: 110-115.
  • 10Leung L F and Tsui C Y. Energy-aware synthesis of networks-on-chip implemented with voltage islands[C]. Proceedings of the 44th Annual Conference on Design Automation, San Diego, 2007:128-131.

共引文献70

同被引文献6

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部