基于FPGA的有源配电网实时仿真器I/O接口设计

I/O Interface Design for FPGA Based Real-time Simulator of Active Distribution Networks

分布式电源、电动汽车及需求侧响应资源的广泛接入使有源配电网动态特性变得更加复杂。对基于实时仿真的有源配电网硬件在环仿真提出了新的需求和挑战。基于FPGA(field programmable gate array)的有源配电网实时仿真器具有仿真步长小、仿真精度高、I/O接口丰富、易于扩展、成本低等优点。面向基于FPGA的有源配电网实时仿真器的多种通信需求,以FPGA自身硬件结构为基础,提出了基于FPGA的有源配电网实时仿真I/O接口的设计框架,并设计了用于接收外部设备模拟信号、具有数字滤波功能的高精度通用A/D接口,用于仿真结果输出的通用D/A接口以及用于实现多FPGA全双工通信的高速光模块接口。同时,针对含光伏发电的有源配电网实现了3μs步长的实时仿真测试,其光照强度信号由光照采集器通过A/D接口输入到仿真器中,仿真结果经由D/A接口输出到示波器显示,通过与PSCAD/EMTDC软件仿真结果的对比,充分验证了I/O接口设计的有效性和正确性。

With the wide integration of distributed generators, electric vehicles and the demand side response resources, active distribution network （ADN） shows great complexity in operation mode and dynamic behavior, which bring new challenges for the real-time simulation platform in hardware-in-the-loop configuration. The FPGA based real-time simulator takes advantage of many merits of field programmable gate array （FPGA）, such as small time-step, high simulation precision, rich I/O interface resources, and low cost. The I/O interface framework of the simulator was proposed to fulfil communication requirement between the simulator and external devices. A universal high-precision A/D converter interface was designed to accept signals from physical devices. A universal high-speed D/A converter interface was designed to output the result signals to physical devices, as well as a high-speed photoelectric converter interface with multiple full duplex channels was presented in application of communication between FPGA boards. A typical low voltage distribution network including photovoltaic （PV） generation unit was simulated in real-time with a time-step of 3μs. The real world irradiance is collected by solar sensor and then imported to the simulator via A/D converter. The results of the simulator were displayed on an oscilloscope via D/A converter. Simulation results were compared with commercial off-lime simulation tool PSCAD/EMTDC to validate the correctness and effectiveness of the I/O interface design.