一种快速响应低压差线性稳压器的设计

Design of a Fast Response Low Dropout Regulator

介绍了一种应用于DRAM芯片内部供电的新型低压差线性稳压器(LDO)。在传统LDO电路PMOS输出驱动管的栅端增加了一个开关电容电路,根据负载电流使能信号控制耦合电容的接入,使驱动管的栅端耦合到一个正向或者负向的电压脉冲,在负载电流急剧变化时能快速调整过驱动电压,以适应负载电流的变化。仿真结果显示,该电路有利于输出电压的快速稳定,恢复时间缩短了38%以上。采用45nm DRAM掩埋字线工艺进行流片。实测结果显示,该LDO输出电压恢复时间在10ns以内。在DDR3-1600的数据传输速度下,DRAM芯片的数据输出眼图为280ps,符合JEDEC标准。

A fast response low dropout regulator （LDO） was presented, which was used in DRAM chip for internal power supply. Based on traditional PMOS type LDO circuit, a switch capacitor circuit was added at the gate of output driving PMOS. This capacitor was dynamic, and it was controlled by current load enable signals. When the LDO current load changed dramatically, this capacitor made the gate of PMOS have a positive or negative pulse, and the LDO output voltage recovered to normal level very quickly, so as to adapt to the current load changes. Simulation results showed that the recovering time could be improved by 38%, which was benefit for fast settling of output voltage. The proposed LDO circuit was taped out in a 45 nm DRAM buried WL process. And test results showed that the recovering time output voltage was within 10 ns. The DRAM chip＇s output data eye was 280 ps at DDR3-1600 speed grade, which met JEDEC standards.