期刊文献+

适用于TIADC的高精度时间失配误差校准算法 被引量:3

A Highly Accurate Calibration Algorithm in Time Mismatch Errors for Time-Interleaved ADCs
下载PDF
导出
摘要 设计了一种适用于TIADC的高精度时间失配误差校准算法。基于相邻通道信号互相关原理,对相邻通道的输出信号作相关运算来估计时间失配误差,再利用基于泰勒级数展开的高阶误差校准方法进行误差校正。误差估计模块与校准模块构成一个反馈环路,可以实现误差的实时跟踪和校正。校准算法行为级仿真结果表明,在12位1GHz四通道的TIADC中,当输入信号归一化频率fin/fs=0.477 1时,校准后系统的ENOB提高到11.85位,SNR提高了43dB以上,校准效果明显。相比已有的校准算法,该校准算法具有更高的校准精度,不受通道数的限制,结构更简单,且在整个奈奎斯特频率范围内都适用,非常适合工程应用。 A highly accurate calibration algorithm in time mismatch errors for time-interleaved ADCs was designed. The algorithm was to estimate the time mismatch error based on the principle of cross-correlation of adjacent channel signals, and a high-order error correction algorithm was used to calibrate the time mismatch error based on Taylor series. Error estimation module and calibration module formed a feedback loop, which could achieve real-time tracking and correcting of error. Through MATLAB simulation, the results showed that for the 12 bit, 1 GHz four-channel TIADC, when the normalized frequency of the input signal fin/f~ was 0. 477 1, and after calibrating, the ENOB was improved to 11.85 bit and the SNR was increased by more than 43 dB, so the calibration effect was obvious. Compared with existing calibration algorithm, the simulation results showed that the proposed algorithm had a higher calibration accuracy and a simpler structure. It was not limited by the number of channels. It was suitable for the applications over the entire Nyquist frequency, especially in engineering applications.
出处 《微电子学》 CSCD 北大核心 2017年第3期406-411,共6页 Microelectronics
基金 中央高校基本科研业务费专项资金资助项目(2014HGCH0010)
关键词 时间交织模数转换器 通道信号互相关 泰勒级数展开 频率判断 Time-interleaved ADC Channel signal cross-correlation Taylor series expansion frequency judgment
  • 相关文献

参考文献2

二级参考文献27

  • 1徐文波,田耘.XilinxFPGA开发实用教程[M].北京:清华大学出版社,2012.
  • 2JR BLACK W C, HODGES D A. Time interleaved con- verter arrays [ M ]. IEEE Journal of Solid-State Circuits, 1980,15 (6) : 1022-1029.
  • 3KUROSAWA N, KOBAYASHI A, MARUYAMA K, et al. Explicit analysis of channel mismatch effects in time-in- terleaved ADC systems [ J ]. IEEE Transactions on Circuits and System I: Fundamental Theory and Applications, 2001,48 ( 3 ) :261-271.
  • 4MANAR E C,BORIS M. Background calibration of time- interleaved data converters [M ]. Springer Science + Busi- ness Media,2012.
  • 5VOGEL C. The impact of combined channel mismatch effects in time-interleaved ADCs [ J ]. IEEE Transactions on Instru- mentation and Measurement ,2005,54( 1 ) :415-427.
  • 6ZHANG P,YE F,YU B,et al. Mixed-signal calibration of sample-time error in time-interleaved ADCs [ J]. Electron- ics Letters, 2011,47 ( 9 ) : 533-535.
  • 7LIU W, CHIU Y. Time-interleaved analog-to-digital con- version with online adaptive equalization [ J ]. IEEE Transactions on Circuits and Systems l:Regular Papers, 2012,59(7) : 1384-1395.
  • 8MATSUNO J, YAMAJI T, FURUTA M, et al. All-digital background calibration technique for time-interleaved ADC using pseudo aliasing signal [ C ]. IEEE International Sym- posium on Circuits and System ( ISCAS ), IEEE, 2012 : 1050-1053.
  • 9ZOU Y X, ZHANG S L, LIM Y C, et al. Timing mismatch compensation in time-interleaved ADCs based on multi- channel Lagrange polynomial interpolation [ J ]. IEEE Transactions on Instrumentation and Measurement,2011, 60(4) :1123-1131.
  • 10LAW C H, HURST P J,LEWIS S H. A four-channel time- interleaved ADC with digital calibration of interchannel timing and memory errors[ J]. IEEE Journal of Solid-State Circuits ,2010,45 (10) :2091-2103.

共引文献19

同被引文献7

引证文献3

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部