基于SRAM软错误失效概率的交织距离选择模型

A Model of SRAM Interleaving Distance Selection with Soft Error Failure Probability

在静态存储器(SRAM)抗辐射加固设计中,单错误纠错码(SEC)联合交织是解决空间SRAM多比特翻转(MBU)的有效方法。交织距离(ID)的选择应当使MBU分布在不同的物理字中,ID越大,电路实现越复杂,功耗和面积也越大。基于SRAM在空间产生的MBU错误图样以及数目,在已有的ID选择模型上进行修正,提出了一种精确的评估模型。

In the radiation hardened design of SRAM, the SEC code combined with interleaving is an effective way to mitigate MBU errors of SRAM in the space. The selection of interleaving distance（ID） should enable MBUs to be distributed in different physical word, but the greater the ID is, the more complex the circuit implementation is, and the power consumption and area are larger as well. Based on the maps and numbers of MBU errors occurred in the space, the existing ID selection model was revised, and a more accurate model was provided to evaluate the failure probability of SRAM in the space.