面向HEVC的高效插值滤波VLSI架构设计

Design of HEVC-Oriented High-Efficiency Interpolation Filtering VLSI Architecture

为满足HEVC(High Efficiency Video Coding)标准解码器中数据高吞吐率和高访存量的要求,提出了一种面向HEVC的高效率分像素插值滤波VLSI(Very Large Scale Integration)架构设计。在HEVC标准分像素插值算法的基础上,构造高并行度和流水线的插值滤波VLSI架构;利用滤波器系数反转对称性,设计可复用8阶滤波器结构,以减少滤波器硬件面积;在传统的单输入通道插值器的基础上,设计两路并行的8输入插值器,以提高数据吞吐量。实验结果表明,该设计能在频率为34.2 MHz下完成1 920×1 080@30帧/s视频解码需求,同时,能够满足3 840×2 160@60帧/s视频的实时传输。

As for HEVC（ High Efficiency Video Coding） standard decoder,high throughput rate and high memory access volume of data serve as bottleneck problems,design of a HEVC-oriented high-efficiency sub-pixel interpolation filtering VLSI（ Very Large Scale Integration） architecture is put forward. Based on sub-pixel interpolation algorithm in HEVC standard,an interpolation filtering VLSI architecture characterized by high degree of parallelism and flow line is constructed. Through utilization of inversion symmetry of filter coefficients,a reusable order-8 filter structure is designed in order to reduce area of filter hardware. On the basis of the traditional single-input channel interpolator,a parallel-channel 8-input interpolator is designed to improve data throughput. Experimental result indicates tha the design can meet decoding requirements of 1 920 × 1 080 @30 f/s video at a frequency of 34. 2 MHz. And this design can meet requirements of real-time transmission of3 840 × 2 160 @ 60 f/s video.