一种降抖动的位同步环路设计与实现

Design and implementation of a symbol synchronization loop to reduce timing jitter

针对通信系统中位定时环路自噪声过大的问题,改进了传统Gardner位同步环路,采用改进型Gardner算法与PSO算法优化的预滤波器相结合的方式,从定时误差检测和波形预处理两方面有效抑制了环路的定时误差抖动,提升了环路收敛速度。通过算法仿真,验证了该改进环路的正确性和有效性;通过FPGA验证,表明了该环路的可实现性和良好的工程应用价值。

To reduce the self-noise of the symbol timing synchronization loop in a communication system , an improvement of the symbol synchronization loop based on the traditional Gardner algorithm is proposed, using modified Gardner algorithm and optimized prefilter by PSO algorithm to effectively suppress the timing jitter and quicken the convergence rate. The correctness and effectiveness of the improved algorithm is verified by the simulation , and the verification on FPGA indicates that it has a great value in engineering application.