LV/HV兼容CMOS芯片与制程结构

LV/HV Compatible CMOS Chip and Process Structure

LV/HV兼容CMOS技术,该技术能够实现低压5 V与高压100~700 V(或更高)兼容的CMOS工艺。为了便于高低压MOS器件兼容集成,采用具有漂移区的偏置栅结构的HV MOS器件。改变漂移区的长度,宽度,结深度以及掺杂浓度等可以得到高电压。采用MOS集成电路芯片结构设计、工艺与制造技术,依该技术得到了芯片制程结构。

LV/HV compatible CMOS technology that enables low voltage 5V and high voltage 100 to 700V （or higher） is compatible CMOS processes. In order to facilitate the integration of high and low voltage MOS devices, a HV MOS device with a bias gate structure with a drift region is adopted. High voltage can be obtained by changing the length, width, junction depth and doping concentration of the drift region. Using MOS integrated circuit chip structure design, process and manufacturing technology, the chip process structure is obtained by this technology.