摘要
基于130 nm CMOS工艺设计了一款特高频(UHF)频段的锁相环型小数分频频率综合器。电感电容式压控振荡器(LC VCO)片外调谐电感总值为2 n H时,其输出频率范围为1.06~1.24 GHz,调节调谐电感拓宽了频率输出范围,并利用开关电容阵列减小了压控振荡器的增益。使用电荷泵补偿电流优化了频率综合器的线性度与带内相位噪声。此外对电荷泵进行适当改进,确保了环路的稳定。测试结果表明,通过调节电荷泵补偿电流,频率综合器的带内相位噪声可优化3 dB以上,中心频率为1.12 GHz时,在1 k Hz频偏处的带内相位噪声和1 MHz频偏处的带外相位噪声分别为-92.3和-120.9 dBc/Hz。最小频率分辨率为3 Hz,功耗为19.2 mW。
An ultrahigh frequency（ UHF） band phase locked loop based fractional-N frequency synthesizer was fabricated in the 130 nm CMOS process. The LC voltage controlled oscillator（ LC VCO）output a frequency from 1. 06 GHz to 1. 24 GHz when the total off-chip tuning inductance value was2 n H. The output frequency range was enlarged by adjusting the tuning inductance,and the gain of the VCO was reduced by using the switched capacitor array. The linearity of the frequency synthesizer and the in-band phase noise were optimized by adding charge pump offset current. A stable performance of the loop circuit was achieved by improving the circuit design of charge pump. Test results show that the inband phase noise of the frequency synthesizer can be optimized more than 3 dB through tuning the charge pump offset current. When the center frequency is 1. 12 GHz,the in-band phase noise at 1 k Hz offset and the out-of-band phase noise at 1 MHz offset are-92. 3 and-120. 9 dBc/Hz,respectively. The minimum frequency resolution is 3 Hz and the power consumption is 19. 2 m W.
出处
《半导体技术》
CSCD
北大核心
2017年第7期505-510,共6页
Semiconductor Technology
