一种JPEG 2000中MQ编码器的VLSI设计（英文）

VLSI Design of MQ Encoder in JPEG2000

提出了1种每周期处理1个(CX-D)数据对的高效的MQ编码器硬件结构.优化概率估计值表,化简了编码逻辑并节省了资源.使用1种基于预测的字节输出结构,减小了路径延时.在FPGA平台上综合该MQ编码器,吞吐率可达到151.7 Msymbols/s.

A high efficient MQ encoder is presented. Proposed MQ encoder can encode one CX-D pairs in every clock cycle. Probability estimation table（PET） is optimized to simplify the algorithm and reduce occupied memory bits. A novel BYTEOUT architecture is proposed using a prediction technique which reduces the path delay. This MQ encoder is implemented on a Xilinx FPGA, it achieves a throughput of 151.7 Msymbols/s.