摘要
为了提高高速调制器的处理速率,给出了一种高速并行调制器的设计方案。该方案将差分编码、成形滤波等处理模块全部转化为并行结构,从而在系统主时钟频率受限的情况下进一步提高了处理速率,并对这些功能模块的实现结构进行了优化,以减少资源消耗,便于FPGA实现。测试结果表明,该方案能够显著提高调制器的处理速率。
In order to improve the processing rate of high-rate modulator, a design scheme of high rate parallel modulator is presented.The scheme transforms all processing modules such as differential coding and shaping filter into parallel structure to improve the processing rate further in the condition of the frequency of system major clock restricted, and optimizes the implementation structure of each function module to reduce the consumption of resources and be easy to the FPGA implementation.The test result indicates that the scheme can improve the processing rate of the modulator significantly.
出处
《电子设计工程》
2017年第13期99-103,共5页
Electronic Design Engineering
关键词
高速
并行结构
调制
FPGA
high-rate
parallel structure
modulation
FPGA
