CCSDS标准低并行度高速LDPC编码方案

An encoder architecture scheme with low parallel and high speed for LDPC codes based CCSDS standard

提出了一种基于CCSDS标准的低并行度高速LDPC编码结构设计方案。该编码结构通过对输入的待编码信息插"0"和改变校验矩阵的循环子矩阵结构实现了CCSDS标准中的7/8码率编码方案的奇偶并行编码,且编码结果奇偶并行输出。在编码器的编码速率需求和编码器实现的硬件资源开销上达到平衡。仿真和实现的结果表明,该低并行度编码结构的设计相对于其他7/8码率串行编码结构设计,在增加少量的硬件开销的条件下,获得双倍的编码速率。

An encoder architecture with low parallel for LDPC codes based CCSDS standard is proposed in this paper. By filling ＂0＂ and changing the cyclic-matrix structure, the proposed scheme implements a low parallel coding for the 7/8 rate LDPC which recommended by CCSDS. The proposed architecture achieves a balance between encode speed and hardware overhead. The results of simulation and implements show that the low parallel architecture has a better encode efficiency and higher encode speed while increasing a few hardware cost.