适于低延迟通信数据链抗干扰传输架构

Architecture to Anti-jamming Transmission for Low Delay Data Links

为满足通信数据链对抗信道误码干扰能力以及低延迟传输特性的需求,设计并实现了一种满足高速信号实时处理要求的低延迟通信数据链数据抗干扰传输架构。通过深入分析算法数学原理,采用全并行流水架构设计,利用深度流水线切割结构中较长组合逻辑路径,在适当增加少量存储器资源开销基础上,大幅度提高了系统工作频率。实验结果表明本文所设计的架构硬件资源消耗少,延迟低,速度快,最高可以实现超过400MPSP处理样本的数据吞吐量,系统实际运算值与理论值完全一致,具有高可靠性。

In order to satisfy demand that the communication data link for the ability of the resist interfer- ence of channel error and character of low delay communication, a anti-jamming communication architec- ture has been designed and implemented that could satisfy requirement of high-speed real-time signal pro- cessing. Through deep analysis mathematical principles of algorithm, structure has been designed based on full parallel pipelining; and longer combinational logic path has been cutting by the depth line in the structure, and so the system working frequency has been improved greatly based on appropriate cost a small amount of storage resources. The experimental results show that the hardware resource consumption of the architecture is low, with the feature of the low delay, high speed, and more than 400MPSP pro- cessing sample of the data throughput has been achieved. The calculated actual results of system are the same with the results of theory completely, with the high reliability of the designed hardware structure.