基于FPGA实现的MU校验仪采样实时接口设计

Design of FPGA-based Sample Real-time Interface of Merging Unit Tester

由于合并单元检验仪的主控DSP的计算任务繁多,计算耗时相对较长,用于数据通信的时间减少,从而影响合并单元校验仪的采样实时性。提出一种基于ADI公司Blackfin DSP BF609的Link Port协议的FPGA接口设计方法,同步时钟最大达到83 MHz,最大数据吞吐率为650 Mb/s,极大地提高了数据通信效率,也提高了合并单元测试仪的采样实时性。

Because of the various computing tasks,the master DSP of the merge unit tester takes a relatively long time on computing,and less time on data communication and hinders the performance of the merge unit tester real-time sampling.To improve the data communication effect of the master DSP,a novel design of high performance data communication interface based on the Link Port protocol of Blackfin DSP BF609 has been put forward,which using FPGA design technique.In the design the largest synchronous clock is up to 83 MHz,and the maximum data throughput rate is 650 Mb/s,which improving the efficiency of data communication and real-time sampling of the merge unit tester.