基于FPGA的PLC浮点运算系统的设计与实现

Design and implementation of PLC floating-point operation system based on FPGA

针对传统PLC应用领域中控制器浮点运算速度慢、精度低的问题,提出了基于FPGA的PLC浮点运算系统的实现方案。根据编译原理设计了程序转化软件IEC_TO_FPGA,实现了IEC 61131-3标准的结构化文本语言到Verilog HDL语言的转换。通过研究IEEE754标准的浮点数的表示及加减、乘除运算规则,利用硬件描述语言Verilog HDL实现了单精度浮点数基本的加减、乘、除的运算功能。在Quartus II环境下,将转换生成的程序进行功能仿真,验证了FPGA-PLC浮点运算系统的可行性。

Aiming at slowness and low accuracy problem o~ traditional PLC floating-point controller, a PLC floating poim op eration system based on FPGA is proposed. According to compilation principle, the program conversion software IEC_ TO _FPGA is designed. The standard IEC 61131-3 structured text language is converted Verilog HDL language. By studying the IEEE754 standard floating-point representations addition and subtraction, multiplication and division rules, the hardware description language Verilog HDL is used to achieve a single-precision floating-point basic addition and subtraction, muhipli cation and division. In the Quartus II environment, the generated program is simulated, which verifies the feasihility of the FPGA-PLC floating point computing system.