基于Zynq的AXI总线数据传输软件优化

A Software Optimization of Data Transmission based on AXI Bus of Zynq

Xilinx Zynq-7000提供了一种ARM+FPGA单片解决方案,非常适合计算密集、功能丰富的嵌入式系统设计。如何通过不同技术路径访问外部接口,逼近理论传输带宽具有重要意义。典型系统应用环境中,采用XC7020作为主控芯片,其集成处理器系统(Processing System,PS)通过AXI总线与可编程逻辑资源(Programmable Logic,PL)相连,其他外设也通过AXI总线接入PS。因为通过系统函数访问AXI总线的性能与理论值相差甚远,所以分别采用SIMD指令、DMA技术和Cache技术对AXI总线访问进行软件优化,并针对64~4 096 Byte大小的包进行分别测试。测试结果表明,经过优化后的访问速率接近AXI总线接口的理论极限。

Xilinx Zynq-7000 provides a ARM＋FPGA monolithic solution quietly suitable for the design of intensive-computing and functionally-embedded system. How to make access to the external interface via various technical approaches and approximate theoretical transmission bandwidth is of great significance. XC7020 is selected as the master chip in typical system application environment, the integrated PS（Processing System） is connected to the PL（Programmable Logic） via AXI bus, while the other peripherals also connected to the PS via the AXI bus. The accessing capability of AXI bus via system function is far from theoretical value, thus the SIMD instruction, DMA technology and Cache technology are used to optimize the software accessing of AXI bus, and the respective test are done for 64 ~ 4096 Byte size packages. The test results indicate that the optimized accessing capability is close to the theoretical limit of AXI bus interface.