基于AHB总线的快速并行CRC算法设计与实现

Design and Implementation of AHB-Based Fast Parallel CRC Algorithm

循环冗余校验(CRC,Cyclic Redundancy Check)以其简单的算法、强大的检错能力和抗干扰能力,广泛应用于通信领域,以提高数据传输的可靠性。为满足高频率的数据传输要求,基于CRC基本原理,介绍了一种快速并行CRC算法,然后采用该算法基于高级高性能(AHB,Advanced High Performance Bus)总线,运用硬件描述语言Verilog HDL设计并实现了CRC计算模块。仿真结果表明,该算法能够在确保数据可靠性的同时提高CRC的计算速度。

On account of simple algorithm and extraordinary error-detecting and anti-jamming capabilines, Cyclic Redundancy Check （CRC） is widely used in data communications in purpose of enhancing data reliability. On the basis of CRC fundamental, a fast parallel CRC algorithm is introduced in the paper to meet the requirements of high-speed data transmission. The algorithm is then used to design a CRC calculation module based on AHB bus system using Verilog HDL. The simulation results indicate that the fast parallel CRC algorithm dramatically improves calculation speed while ensuring the data reliability.