1553B容错解码器对抗干扰的可信赖性改进

Improved Reliability of 1553B Fault Tolerant Decoder Against Interference

通过1553B通信协议各种解码器设计方案讨论了引起协议可信赖性不足的硬件的三个原因:没有对干扰的容错设计,拖尾电压超过输入下限以及缺少过0位置的修正能力。所以解码器容错能力的提高是改善1553B通信协议可信赖性的关键。文中介绍了容错解码器中对抗干扰的部分:将每8slot组成两个半位HB1和HB2。采用这种方法,在半位中连续干扰宽度为3slot的可以排除掉,宽度小的干扰累加小于3时也可滤除掉。对于增频的1553B芯片(例如2Mbps以上),这是更加重要的可信赖性改进。

By discussing various 1553B decoder design, three hardware dependability defects are found= no fault tolerance design against disturbance, tail-off voltage higher than low range input threshold and lack of adaptation to zero-crossing change caused by disturbance. Hence the fault tolerance design of decoder is the key element to improve 1553B dependability.The anti-disturbance part of new design is disclosed in the paper.The new design can tolerant up to 3 slots disturbances. This is more important for enhanced 1553B chip which works at 2 Mbps or more.