自动闭塞逻辑检查电路设计

Design of Logic Check Circuit of Automatic Block System

结合既有的自动闭塞区间继电式逻辑检查通用电路,对自闭区间多分割闭塞分区和进站分界时的逻辑检查电路设计、逻辑检查新增继电器的条件电源设置、集中联锁车站对管辖中继站逻辑检查总报警条件的设置等工程设计问题,进行了分析探讨,给出了设计方案,并对逻辑检查操作表示电源进行了简化设置。

Combined with the existing general-purpose circuit of relay logic check for automatic blocking section, several problems of engineering design including design of logic check circuit for block section with multiple cut sections and section demarcated by home signal, setting of conditional power supply of added relay for logic check, whole warning condition setting of relay station controlled by interlocking station etc. are analyzed and discussed. Design schemes are presented and simplified setting of power supply for operation and indication of logic check is also given.