多核片上系统时钟网络结构模型与仿真分析

Clock Network Structure and Simulation on MPSoC

对多核片上系统(MPSoC)而言,随着集成度和性能的提升,时钟网络的结构愈发重要。研究了基于结构建模的多路全局/局域时钟网络的结构建模与分析。通过建立多级级联,分别从主干、支干和接入三层对时钟网络的结构进行建模。针对运算单元接入数、单行中肋排数目、运算单元中输入时钟数目以及时钟区域数等几方面,评估了时钟网络性能。以Stratix V E FPGA为例对时钟网络综合分析,分析结果表明,四象限的对称结构权衡了多项性能指标,是最优的时钟网络结构,可以作为一种通用结构应用在目前主流MPSoC上。

Flexibility is becoming more and more important to the overall performance of modern MPSoC clock networks. The flexibility of global and local networks based on structural modeling is studied. Through the es- tablishment of multi-level structure, the structure is separated into three layers, i.e. trunk, branch and access. The performance of clock network is evaluated in terms of the number of logical blocks, the number of rows in a single row, the number of logic element input clocks in the logic block, and the number of clocks. Stratix V E FPGA is taken as an example of a comprehensive analysis of the clock network, and the analysis results show that the four quadrant symmetric structure is the optimal clock network structure by fully considering about the tradeoff of overall performance, and can be used as a general structure in the current mainstream MPSoC.