基于三角函数内插法的Gardner位定时同步环的FPGA实现

FPGA implementation of Gardner Bit timing synchronization loop based on trigonometric polynomial interpolation

位定时同步是全数字接收系统中的关键组成部分,对系统性能有重要影响。Gardner定时同步环结构简单便于工程实现,三角函数内插法结构简单内插精度高。文章将三角函数内插法应用于Gardner定时同步环,降低了实现难度。

Bit timing synchronization is one of the key component of all digital receiver, which directly affects the performance of the system. Gardner timing recovery loop has a siraple structure, which is easy for engineering realization, trigonometric polynomial interpolation has a simple strncture and enjoys high interpolation performance. In this paper, trigonometric interpolation method is applied to Gardner Bit timing synchronization loop and it reduces the difficulty of implementation.