改进型CIC抽取滤波器的FPGA实现

FPGA-based implementation of modified CIC decimation filter

为了解决以往设计的CIC抽取滤波器存在的数据速率高以及功耗高的问题,研究了改进型CIC抽取滤波器的FPGA实现过程,优化CIC抽取滤波器硬件实现结构,采用FPGA实现抽取滤波器的设计。分析CIC抽取滤波器的硬件实现结构和位宽,通过Hogenauer抽取滤波器结构,得到6级16抽取的CIC硬件实现结构,将该结构变换成4个CIC抽取滤波器的级联式FPGA实现,逐级降低数据速率,提升数据位宽。以FPGA实现CIC抽取滤波器过程中,分析了其运算时寄存器所需的最高位宽,避免产生数据溢出问题。实验结果表明,所设计的改进型CIC抽取滤波器是有效的,可降低数据速率和系统功耗。

In order to reduce the data rate and power consumption of the previously-designed CIC decimation filter, the FPGA- based realization process of the improved CIC decimation filter is studied, the hardware implementation structure of the CIC decimation filter is optimized, and FPGA is used to design the decimation filter. The hardware implementation structure and bit wide of CIC decimation filter are analyzed. The filter structure is decimated through Hogenauer to get the CIC hardware imple- mentation structure whose decimation rate is 16 and decimation degree is 6. The structure is transformed into four cascaded CIC decimation filters implemented with FPGA, which can reduce the data rate and improve the data bit wide. In the implementation process of CIC decimation filter with FPGA, the highest bit wide required by the register while it is operating is analyzed to avoid the data overflow problem. The experimental result shows that the modified CIC decimation filter is effective, and can reduce the data rate and system power consumption.