基于最小门延迟的时间数字转换器设计

Design of a time-to-digital converter based on the minimum gate delay

设计了一种基于最小门延时的时间数字转换器(TDC),该TDC采用游标延迟链结构。在传统的基础上,利用电压比较器产生一个上升沿陡峭的阶跃信号,作为时间测量的内部传输信号,减少了信号在门延时的翻转时间并且降低了功耗。相位判别采用Arbiter电路,提高了时间判断的准确性。利用半静态双边沿D触发器构成了16进制计数器,扩展了测量时间的动态范围,同时降低了功耗。在TSMC 180 nm工艺,1.8 V电源电压下完成整个设计,仿真结果表明,TDC的分辨率为5.3 ps,动态范围为7.2 ns,功耗为6.5 mW,面积为0.18 mm^2。

A time-to-digital converter（TDC） is designed based on the minimum gate delay, a vernier delay chain structure was adopted in the TDC. On the basis of the traditional structure, a steep rising step signal was generated by a voltage comparator, the signal is used as the internal transfer signal for time measuring, such that the power consumption is reduced and the turnover time of gate delay is decreased. The Arbiter circuit was used as phase discrimination, the time measurement accuracy was improved. The hexadecimal counter was designed by using semi-static double edge-triggered flip-flops, it not only extended the dynamic range of time measuring, but also reduced the power consumption. The TDC is designed in TSMC 180 nm CMOS technology with 1.8 V power supply, the simulation result shows that the resolution is 5.3 ps, dynamic range is 7.2 ns, the average power consumption is 6.5 m W and the area is 0.18 mm^2.