JPEG编码器的设计与VLSI实现

Design and VLSI implementation of JPEG encoder

随着图片和视频的信息量变得越来越大,对这些信息进行压缩和存储十分必要,设计了一种高性能的联合图像专家组(JPEG)图像编码器。首先,采用Verilog HDL语言对JPEG中二维离散余弦变换(DCT)、量化以及熵编码等关键模块进行了建模,并对各个模块分别进行了仿真和验证,通过比较MATLAB和Modelsim的仿真结果验证所设计功能模块的正确性;在此基础上,完成了JPEG编码器的整体设计,并选取标准测试图片对其进行功能验证,通过比较原始图片和重建JPEG图像得到PSNR值,验证结果表明所设计的JPEG编码器满足应用需求;最后,对JPEG编码器进行了超大规模集成电路(VLSI)硬件实现,在SMIC180 nm工艺下,用Synopsys Design Compiler对设计进行综合,用Cadence SOCEncounter对综合后的门级网表进行布局布线,物理实现结果如下:工作在100 MHz下,芯片的功耗为460 mW,最终布局布线之后的面积为10.7 mm^2。所设计的编码器可以作为IP核应用于其他图像或者视频处理芯片之中。

Owing to the larger information ol images and videos,it is necessary to compress these information. By analyzing the Joint Photographic Experts Group （ JPEG） compression standard,this paper implements a high per-formance whole process design of JPEG picture encoder. Firstly,the 2D discrete cosine transform（ DCT）, quantiza-tion and entropy coding modules were modeled using Verilog HDL language. Then,each module was simulated by Modelsim and verified by comparing with MATLAB results separately. The compared results show that all of the de-veloped modules are correct. After that,the whole JPEG encoder was designed and verified by using standard test images. The PSNR was obtained by comparing the original image with rebuilt JPEG image. The results show that this JPEG encoder can satisfy the application requirement. Finally,the very large scale integration （ VLSI） imple-menting of the proposed JPEG encoder was developed. The encoder was synthesized by using synopsys Design Com-piler and routed and placed by using Cadence SOC Encounter under the process of smic180 nm. The physical im-plementation results are as follows ： The total power is 460 mw at working frequency 100 MHz and the total area is 10.7 mm2. Furthermore,this design can also be used as an IP core in other image and video processing chips.