高速大容量数据记录仪的无效块信息列表动态刷新算法设计

The Design of Invalid Block Information List Dynamic Refresh Algorithm of High Speed and Large Capacity Data Recorder

针对流水线技术构建的高速大容量存储阵列,设计了一种基于FPGA的"无效块信息列表动态刷新算法"。系统以NAND型Flash为存储介质,以FPGA为逻辑控制中心,在其内部建立一个一维RAM实现了高速大容量存储系统的无效块信息的记录。仿真结果及可行性分析验证了"无效块信息列表动态刷新算法"的可行性,该算法建立的无效块信息列表的容量不受存储容量扩展的影响,减少了对FPGA内部资源的占用,在满足大容量存储的同时,且不影响高速存储。

Due to high speed and large capacity memory array for pipeline technology＂invalid block information list dynamic refresh algorithm＂based on FPGA is designed.The system takes the NAND Flash as the storage medium,its core is FPGA logic control,establishing a one-dimensional RAM in its interior realizing the detection information of invalid block of high speed and large capacity storage system.Simulation and feasibility analysis results show that its feasibility,The capacity of the invalid block information list established the algorithmis isn’t affected by the expansion of storage capacity.It reduces the occupation of the internal resources of FPGA,at the same time to meet the large capacity storageand don’t affect high speed storage of the system.